IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST)

December 15-17, 2020
Virtual (IIT Kharagpur)
Kolkata, India

Zoom link
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Proceedings: Click to download


  • 10:00PM - 11:00PM India Time (11:30AM - 12:30PM EST) (12:30AM - 01:30AM Beijing Time)
    SHORT PAPER SESSION
    Session Chair: Shivam Bhasin (sbhasin@ntu.edu.sg), NTU Singapore
    • Protecting Platoons from Stealthy Jamming Attack
      Yaodan Hu, Haoqi Shan, Raj Gautam Dutta and Yier Jin - University of Florida, USA
      Speaker: Yaodan Hu
      Short bio: Yaodan Hu is a PhD student of Dr. Yier Jin in the Department of Electrical and Computer Engineering, the University of Florida. Her research interest focuses on the cyber-physical system security and resilience and smart grid security.
      Abstract: Connected vehicles of a platoon broadcast basic safety messages (BSMs) over the control channel of dedicated short-range communication (DSRC). Nevertheless, the fixed frequency of the control channel makes the communication protocol vulnerable to jamming attacks and consequently hindering the stability of the platoon. In this paper, we investigate the impact of \textit{stealthy} jamming attack on platoon stability. A stealthy jamming attack is one that only jams platoon vehicles with a specific probability, decided based on the risk of being detected. We show via simulation that the maximum distance error induced by the attack is up to eight times more than without attacks. Due to the stealthy nature of the attack, traditional threshold-based detection methods that monitor PLR and MAC-based methods that require high attack probability cannot effectively detect such attacks. To detect the stealthy jamming attack, we propose a mechanism that utilizes the received power and the transmission delay of the signal causing interference as features in Quadratic Discriminant Analysis (QDA), to distinguish the jamming attack from normal interference. We use software-defined radios (SDRs) and the Plexe simulator to demonstrate the feasibility of our stealthy attack and detection mechanism.
      Keywords: Vehicle Platoon, Stealthy Jamming, DSRC, Quadratic Discriminant Analysis, SDR, Plexe
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    • Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing
      Yuan Liu and Pingqiang Zhou - ShanghaiTech University, China
      Speaker: Yuan Liu
      Short bio: Yuan Liu received the B.E. degree from Xidian University, Xi an, China in 2018. He is pursuing the master degree with ShanghaiTech University, Shanghai. His interests include security of deep learning and hardware.
      Abstract: We get three observations from the bit-plane and based on these observations, we proposed the bit-plane classifiers, which take the bit-plane of image as input for classification. To further increase the robustness of classification, we also apply the ensemble decisions to combine different bit-plane classifiers with target model. Experiments show that our method can effectively defend against the adversarial attacks.
      Keywords: adversarial defense,scurity of neural networks,bit-plane slicing
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    • Malware Classification Through Attention Residual Network based Visualization
      Diangarti Bhalang Tariang, Sri Charan Birudaraju, Ruchira Naskar, Vijeta Khare and Rajat Subhra Chakraborty - IIT Kharagpur, IIEST Shibpur, Adani Institute of Infrastructure Engineering, India
      Speaker: Ruchira Naskar
      Short bio: Dr. Ruchira Naskar is an Assistant Professor at IIEST Shibpur, India. Previouslyshe had been affiliated with NIT Rourkela, India. She earned her PhD ComputerScience and Engineering from IIT Kharagpur in 2014. Major area of her researchinterest is Cyber Security and Digital Forensics. She has recently received theBRNS Young Scientist Research Award and the SERB Early Career ResearchAward. Her research works have been published in journals and conferences ofinternational repute. She has been associated with multiple research projectssanctioned by agencies including DST, SERB, CSIR, BRNS.
      Abstract: With the exponential growth of malware variants nowadays, malware detection poses to be an active field of research related to computer security. Traditional methods of malware detection and classification such as static program analysis and dynamic execution analysis, usually combined with machine learning, are restricted due to difficulties of reverse–engineering the program executables, real–time execution trace collection, and manual construction of effective feature sets. Malware classification based on representation of the binary executables as images, followed by advanced machine learning techniques such as deep learning, has been explored to overcome these shortcomings. In this work, we propose a malware classification technique based on malware visualization using an Attention Residual Network (a specialized convolutional neural network), with RGB and grayscale image representations of the malware program binaries. Experimental results for two common malware datasets establish the effectiveness of the proposed neural network in malware classification, even when trained with imbalanced datasets.
      Keywords: Malware Classification, Malware Image Visualization, Deep Learning, Attention Residual Network
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    • Characterization of Electromagnetic Fault Injection on 32-bit Microcontroller Instruction Buffer
      Oualid Trabelsi, Laurent Sauvage and Jean-Luc - Télécom Paris, Institut Polytechnique de Paris, France
      Speaker: Oualid Trabelsi
      Short bio: Oualid Trabelsi is a PhD student within Télécom Paris, which is part of Institut Polytechnique de Paris in France. His doctoral research investigates the development and implementation of methods to characterize the impact of electromagnetic fault injection within devices as FPGAs, test chips and processors Oualid can be contacted at oualid.trabelsi@telecom-paris.fr
      Abstract: Characterizing the sensitivity of microcontrollers is still a high topic, and which the main purpose is to lead to the design of efficient counter-measures againts the observed fault models. In this presentation, we will give the methodlogy used to identify the impacted architecture part of a 32-bit microcontroller through electromagnetic fault injections EMFI. We will highlight through dedicated test codes the feasibility to observe the induced fault models at bit level. In particular, we demonstrate how it is possible to target a specific instructions among those contained in the instruction buffer, by playing with electrical and spatio-temporal parameters of the EMFI setup.
      Keywords: Electromagnetic fault injection, Fault models, Characterization, Microcontroller
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    • PUF Based Secure Framework for Hardware and Software Security of Drones
      Vishal Pal, Bharadwaj Amrutur, Ashish Joglekar, Srikrishna Acharya, Somesh Shrivastav and Sourav Saha - Indian Institute of Science, India
      Speaker: Vishal Pal
      Short bio: Vishal Pal is a serving member of the Indian Armed Forces since 2011. He has obtained Bachelors of Engineering in Electronics and Telecommunication from the University of Pune in 2009. In 2012, he completed his Post Graduate Diploma in Aeronautical Engineering from Visvesvaraya Technological University, Karnataka. He obtained MTech in Microelectronics and VLSI Design from Indian Institute of Science, Bangalore in 2020. In his service to the nation , he has successfully led the technical team in the intercontinental military exercise Red Flag in 2016. He has been awarded by Air Officer Commanding -in-Chief , Western Air Command in 2018 for his distinguished contribution towards Aerospace Safety.
      Abstract: Unmanned Aerial Vehicles (UAVs) augmented with sensors like cameras, GPS and LiDARs, shows tremendous potential in delivering Internet of Things (IoT) services from great heights. Current security challenges in the drone deployment for such applications are: software and hardware breaches, identification of rogue drones and link hijack avoidance. In this work, we extend the secure framework for not only software, but also for hardware breaches and identification of compromised drones using a Trusted Execution Environment (TEE) created by ARM's TrustZone technology and Physically Unclonable Function (PUF). The PUF based unique fingerprints of on-board sensors, flight controller and companion computer of the drone are implemented in a Field Programmable Gate Array (FPGA). The PUF based drone authentication algorithm has been implemented and demonstrated in a proof of concept system and can be incorporated in drone deployments.
      Keywords: Physically Unclonable Function, fingerprint, drones, FPGA, ring oscillator, authentication, IoT
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    • MIDAS: Model Inversion Defenses Using an Approximate Memory System
      Qian Xu, Md Tanvir Arafin and Gang Qu MIDAS - University of Maryland, College Park, Morgan State University USA
      Speaker: Qian Xu
      Short bio: Qian Xu is the fourth-year Computer Engineering Ph.D. student in University of Maryland, College Park. She works with Professor Gang Qu in Institute for Systems Research in UMD. Her main research interests are in hardware security, low power and energy efficient system design and machine learning.
      Abstract: First, we demonstrate that an ML algorithm’s execution flow in physical hardware can be leveraged to secure a trained model. Then, we find that approximate main memory, such as undervolted DRAMs, are useful in adding noise in a loaded model. Next, we design a secure algorithm MIDAS that ensures the safe execution of an ML algorithm under the presence of an adversary. After that, we evaluate MIDAS in terms of model accuracy degradation and similarity metrics.
      Keywords: Hardware Oriented Security, Deep Neural Network (DNN), Model Inversion Attack (MIA), Dynamic Random Access Memory (DRAM)
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    • Defense against On-Chip Trojans Enabling Traffic Analysis Attacks
      M Meraj Ahmed, Abhijitt Dhavlle, Naseef Mansoor, Purab Sutradhar, Sai Manoj Pudukotai Dinakarrao, Kanad Basu and Amlan Ganguly - Rochester Institute of Technology, George Mason University, Minnesota State University, The University of Texas at Dallas, USA
      Speaker: M Meraj Ahmed
      Short bio: M Meraj Ahmed is currently pursuing his Ph.D. at Rochester Insti-tute of Technology, USA. His research interest includes designing energy-efficient and low latency broadcast-oriented interconnection architecture for multicore, multichip communication. He is also interested in designing a secure and reliable mm-Wave multichip wireless communication.
      Abstract: Interconnection networks for multi/many-core processors or server systems are the backbone of the system as they enable data communication among the processing cores, caches, memory and other peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core processors are increasing due to the increasing presence of third party players in a System-on-chip (SoC) design. Even by deploying na ̈ıve HTs, an adversary can exploit the Network-on-Chip (NoC) backbone of the processor and get access to communication patterns in the system. This information, if leaked to an attacker, can reveal important insights regarding the application suites running on the system; thereby compromising the user privacy and paving the way for more severe attacks on the entire system. In this paper, we demonstrate that one or more HTs embedded in the NoC of a multi/many-core processor is capable of leaking sensitive information regarding traffic patterns to an external malicious attacker; who, in turn, can analyze the HT payload data with machine learning techniques to infer the applications running on the processor. Furthermore, to protect against such attacks, we propose a Simulated Annealing-based randomized routing algorithm in the system. The proposed defense is capable of obfuscating the attacker’s data processing capabilities to infer the user profiles successfully. Our experimental results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from>98% to<15% in multi/many-core systems.
      Keywords: NoC, obfuscation, routing, hardware trojan
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    • Compact and Secure Generic Discrete Gaussian Sampler based on HW/SW Co-design
      Sudarshan Sharma, Arnab Bag and Debdeep Mukhopadhyay - IIT Kharagpur, India
      Speaker: Arnab Bag
      Short bio: Arnab Bag is currently pursuing Ph.D. degree in the Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India. He completed his undergraduate degree in the Department of Electronics and Electrical Communication Engineering from the same institute. His research interests include hardware security, public key cryptography and VLSI design.
      Abstract: In this paper, we present the first Hardware (HW)/Software (SW) co-design based generic discrete Gaussian sampler architecture on the Xilinx Zynq platform. The area optimized and secure sampler can produce a distribution based on an arbitrary standard deviation and center given as input. We use multi-level logic optimization on Knuth-Yao algorithm’s Discrete Distribution Generating (DDG) tree travel-based Boolean mapping of random bits and samples instead of the previous two-level logic optimization to reduce the resource utilization. This method results in nearly 60% less LUT utilization compared to the previous designs on Xilinx FPGAs. Further, we introduce improvements in the shuffling algorithm leveraging the HW/SW co-design methodology compared to the existing shuffling architectures for randomizing Gaussian samples to protect against timing-based side-channel attacks.
      Keywords: Discrete Gaussian Sampler, HW/SW Co-design, Knuth-Yao Algorithm, Shuffling based countermeasure, Multilevel logic optimization
      View the slides        View the paper