December 16, 2024 (DAY 0) (All Time in Japan Standard Time)
5:30 PM - 9:00 PM Registration & Reception
December 17, 2024 (DAY 1) (All Time in Japan Standard Time)
9:00 AM - 9:20 AM
Opening Remarks
9:20 AM - 10:10 AM
Keynote 1 Session Chair:Makoto Nagata Speaker: Bart Preneel (COSIC, KU Leuven) Title: Cryptography and Supply Chain Security
10:10 AM - 10:30 AM BREAK
10:30 AM - 11:30 AM
Regular Paper Session 1: Physical Phenomena for Hardware Security Session Chair:TBA
Unveiling Security MRAM-OTP Macro Using MTJ Hard Breakdown Mechanism Jiongzhe Su, Haoran Du, Quanhai Zhu, Mingtao Chen, Keyang Zhang, Bo Liu, Hao Cai- National ASIC System Engineering Center, School of Integrated Circuits, Southeast University
A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator Tuan Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham - The University of Electro-Communications
Truly Random Number Generation by Using In-Plane Magnetic Tunnel Junction with Weak Anisotropy You Wang, Chaoyue Zhang, Yu Gong, Hao Cai, Weiqiang Liu - Nanjing University of Aeronautics and Astronautics, Southeast University
LUNCH BREAK
1:00 PM - 1:50 PM
Keynote 2 Session Chair: Yuichi Hayashi Speaker: Katsumi Takahashi (Nippon Telegraph and Telephone Corporation) Title: Security R&D from a Telecommunication Company
High Reliable Processor-Based PUF on Voltage Over-Scaling Technique Xinyuan Zhao, Yijun Cui, Fei Lyu, Chongyan Gu, Chenghua Wang, Weiqiang Liu - Nanjing University of Aeronautics and Astronautics, QUEEN'S UNIVERSITY BELFAST
Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF Anurag Kamal, Vishesh Mishra, Sparsh Mittal, Mahendra Rathor, Chandan Kumar, Urbi Chatterjee - IIT Kanpur, IIT Roorkee, DAVV Indore
A Novel FPGA Mutually Coupled Configurable Ring Oscillator PUF James Moore, Jack Miskelly, Maire O'Neill, Chongyan Gu - Electronics Communications and Information Technology, ECIT, Queen’s University Belfast, Belfast, U.K
AutoGuard: A Secure Implementation of the Conditional Branch Instruction Zeru Lan, Chunlu Wang, Pengfei Qiu, Yu Jin, Yihao Yang, Dongsheng Wang, Xiaoyong Li, Gang Qu - Key Laboratory of Trustworthy Distributed Computing and Service (BUPT), Ministry of Education, Beijing, China, Department of Computer Science and Technology, Tsinghua University, Zhongguancun Laboratory, Beijing, China, Department of Electrical and Computer Engineering & Institute for Systems Research, University of Maryland, USA * Best Paper Award Candidates.
Automated Search of Instructions Vulnerable to Fault Injection Attacks in Command Authorization Checks of a TPM 2.0 Implementation Ville Yli-Mayry, Thomas Perianin, Sylvain Guilley - Secure-IC K.K., Secure-IC S.A.S. * Best Paper Award Candidates.
Analysis and Mitigation of Hybrid CMOS/MRAM DFF Vulnerabilities to Laser Fault Injection Raphael Comps, Jean-Baptiste Rigaud, Jean-Max Dutertre - Mines Saint-Etienne, CEA, Leti, Centre CMP F - 13541 Gardanne France
A Black-Box Targeted Misclassification Attack on Edge AI with Adversarial Examples Generated from RAW Image Sensor Data Bowen Hu, Weiyang He, Kuo Wang, Chip-Hong Chang- Nanyang Technological University * Best Paper Award Candidates.
December 18, 2024 (DAY 2) (All Time in Japan Standard Time)
9:00 AM - 9:10 AM
Announcement
9:10 AM - 10:00 AM
Keynote 3 Session Chair: Weiqiang Liu Speaker: Patrick Schaumont (Worcester Polytechnic Institute) Title: Practical Security Models for Cryptographic Chip Design
10:00 AM - 10:20 AM BREAK
10:20 AM - 11:40 PM
Regular Paper Session 4: Advanced Physical Attacks (2) Session Chair:TBA
Power Side-Channel Key Recovery Attack on a Hardware Implementation of BIKE Luke Beckwith, Huizhen Zhou, Jens-Peter Kaps, Kris Gaj - George Mason University
Exact Template Attacks with Spectral Computation Meriem Mahar, Maamar Ouladj, Sylvain Guilley, Hacène Belbachir, Farid Mokrane - CERIST, Algeria and Université Paris 8, LAGA, UMR 7539, France, CEntre de Recherche sur l'Information Scientifique etTechnique (CERIST), Algeria, TELECOM-ParisTech, Secure-IC S.A.S. Rennes and ENS Paris, RECITS Laboratory, Mathematics faculty, USTHB, Algiers, Algeria, Université Paris 8, LAGA, UMR 7539, France
Yet Another Physical Leakage Assessment with the Wasserstein Distance Haruka Hirata, Yusaku Harada, Yuko Hara, Kazuo Sakiyama, Yang Li - The University of Electro-Communications, Institute of Science Tokyo
A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation Kazuki Monta, Rikuu Hasegawa, Takafumi Oki, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Norman Chang - Secafy Co., Ltd., Kobe University, ANSYS
LUNCH BREAK
1:00 PM - 1:50 PM
Keynote 4 Session Chair:Yier Jin Speaker: Rui Hou (Institute of Information Engineering, Chinese Academy of Sciences) Title: The Security Architecture Design for General-Purpose Processors
1:50 PM - 3:10 PM
Regular Paper Session 5: Security and Verification in RISC-V and Embedded Systems Session Chair:TBA
A Consistency Testing Method for Revealing RISC-V Processor's Undocumented Instructions Wen Wang, Peng Liu - College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China
Secure and Scalable UVM Verification Components (UVCs) to Accelerate Functional Verification of RISC-V Based SoCs Muhammad Yasir Farooq, Haroon Waris, Nasir Mohyuddin, Sajid Baloch, Yu Gong, Weiqiang Liu - Institute of Space Technology, Islamabad, Pakistan, Centres of Excellence in Science & Applied Technologies, Nanjing University of Aeronautics and Astronautics, Nanjing, China
SecRiSBen: A RISC-V Based SoC Benchmark for Evaluation of Security Verification Tools Maoyuan Cai, Aijiao Cui, Yier Jin - Harbin Institute of Technology (Shenzhen), University of Science and Technology of China
PreLock: Precision Locking for Protecting Embedded Processor Tomosuke Ichioka, Yohei Watanabe, Yuko Hara - Tokyo Institute of Technology, The University of Electro-Communications
